The N4880A reference clock multiplier fills a critical requirement for R&D and test engineers who need to characterize and release the next generation of PCI Express main boards, MIPI M-PHY chipsets and SD card UHS-II host devices. With its support for multiple reference-clock rates, the N4880A will help you accurately characterize and verify standards compliance under easy-to-reproduce test conditions.
Lock the stressed-pattern generator to a system reference clock
In common reference-clock architectures, where the host cannot be driven by an external reference clock it’s necessary to lock the stressed-pattern generator to the same system reference clock used by the receiver under test. This is because the receiver under test also derives its sampling clock from this reference clock. Locking the stressed pattern generator to the same reference clock as the receiver under test ensures accurate and reproducible jitter-tolerance test results.
Get the most precise and reproducible receiver tolerance test results for PCI Express mainboards, MIPI M-PHY and SD UHS-II hosts
The N4880A provides a multiplying phase-locked loop (PLL) which enables users to lock the pattern generator of J-BERT N4903B or ParBERT 81250A to a system reference clock. Spread Spectrum Clocking (SSC) and low frequency jitter are fed through the N4880A up to its PLL loop bandwidth of 2 or 5 MHz. The N4880A tolerates huge amounts of SSC for UHS-II reference clocks and offers excellent input sensitivity to handle very low voltage levels.
Increase your R&D efficiency with a future-proof investment
By using N4880A for receiver test, R&D engineer’s efficiency is increased as the test complexity is reduced by eliminating complicated and time-consuming work-arounds. The R&D investment is secured by usage for multiple emerging standards.
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