B4623B Bus Decoder for LPDDR, LPDDR2, LPDDR3, LPDDR4* Debug and Validation

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Accelerate your time to insight using the B4623B bus decoder for LPDDR, LPDDR2, or LPDDR3 debug and validation. The B4623B provides complete protocol decode of memory transactions using an Keysight logic analyzer as the analysis execution engine. (Select your logic analyzer module depending on your system data rate.)

The B4623B protocol-decode software translates acquired signals into easily understood bus transactions showing associated data bursts, for all LPDDR, LPDDR2, or LPDDR3 data rates. Valid Read and Write commands are decoded to include Row and Column Addresses and the complete data burst associated with the command. The B4623B bus decode software anticipates key system attribute inputs (Burst length, CAS Latency and CAS Write Latency, Chip Selects) from default LPDDR, LPDDR2, or LPDDR3 probing configurations and/or DDR Setup Assistant tool to accelerate decode of LPDDR, LPDDR2, or LPDDR3 bus signals.

• Decodes LPDDR, LPDDR2, or LPDDR3 acquired traces on Keysight logic analyzer or off-line
• Displays commands, protocol transaction type, physical/row/column/bank addresses, and data in the listing viewer 
• Data is displayed at any level of detail from protocol to binary
• Anticipates key system attribute inputs from default probing configurations and/or DDR Setup Assistant tool 
• Allows user input to customize system attributes