U4305A PCIe Exerciser & PCIe LTSSM Exerciser

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PCIe® - PCI Express and PCIe are registered trademarks of PCI-SIG.

Keysight´s PCIe Protocol Analyzer is a combination of hardware and software features that ensure the fastest time to insight.

Thorough link testing

The U4305A PCIe 3.0 Exerciser with pre-defined LTSSM test cases can help validate the complex and hard to test state transitions of DUT´s LTSSM. With the ability to emulate either a root complex or an end point in the same card, the U4305A PCIe 3.0 exerciser can help you validate your device whether it is a server or an add-in card. The emulated personality is easily switched through a simple software switch. The LTSSM test cases come with detailed reporting to clearly define the source of the failures, if found, for fast debug.

NVMe testing

Keysight’s NVMe emulator allows users to test devices and create operational scripts that will allow hardware and software developers to simulate a host root complex. The emulator is able to test all of the NVMe functions of a storage device and from queue management to sending traffic loads to create test scenarios to prove device operation.

Aside from the pre-defined LTSSM test cases, the U4305A PCIe 3.0 Exerciser can be controlled also through an built-in API interface, which is backward compatible with Keysight’s PCIe 2.0 Exerciser. This allows customers to leverage test cases they have already developed for maximum investment protection.

Hardware support

• Supports 2.5 GT/s (Gen1), 5.0 GT/s (Gen2) and 8.0 GT/s (Gen3) speeds
• Link width support x1 through x16 lanes
• Standard PCIe Half size card form factor, to fit into most platforms

LTSSM Software capabilities

• Pre-defined LTSSM tests to help validate the complex and hard to test state transitions of the DUT’s LTSSM
• Detailed reporting to clearly define source of problem for faster debug
• Easy to use test architecture, single click to run all tests

NVMe Root Complex (RC) Emulation

• Scan and initialize the NVMe registers, queues, and interrupts
• Configure submission queue Head and Tail pointers and completion queue head pointer
• Add NVMe commands to submission queues and submit these to the NVMe DUT. The commands are available as predefined templates
• Create PRP lists and PRP entries that can be used in the submitted NVMe commands for data transfer